Scan-based testing is widely used in Very Large Scale Integration (VLSI) circuits. Such scan-based testing involves incorporating scan chain circuit paths into designed circuits such that scan test patterns can be applied to assess proper operation of the flip-flops and gates included in such circuits. Scan chain circuitry can typically cover 10-40% of the total circuit area of a VLSI circuit.
In general, power consumption during scan-based testing is much higher than power consumption during typical operation of a VLSI circuit. Depending upon the scan test pattern applied and the cells of the VLSI circuit to which it is applied, a power drop or local hot spot can develop. This is due in part to the various standard cells included in the circuit having different power consumption due to driving strength, size, and other design characteristics, as well as combinations of data transitions that might occur during application of a scan test pattern that would typically not occur during normal operation. Power drop or local hot spots can result in a determination of a false failure of the circuit, or may even cause permanent damage to the circuit under testing. Accordingly, minimizing the possibility of local hot spots from occurring is preferable.
To address the possibility of such local hot spots, various approaches have been taken for purposes of designing scan chains. Generally, for a given circuit design, a scan chain is inserted such that the scan length (number of flip flop transitions through the scan chain) and/or scan wire length is minimized in an effort to minimize hot spots (e.g., by reducing transitions). However, this often results in localized scan chains within the circuit, leading to the potential of localized hotspots if a scan test pattern results in a large number of flip flop state transitions during a scan test. Furthermore, once scan chains are designed for a circuit, a test pattern is applied and power consumption is estimated, based on an assumption that all scan chains are active at one time. This is based, for example, on an intended test pattern to be applied. If a power budget is exceeded, one or more scan chains can be shifted and a power budget can be reassessed until test power is no longer an issue. However, shifting of scan chains may be inadequate to adjust an overall power budget. Furthermore, because one specific scan chain may involve the greatest amount of power consumption, hot spots may develop within the circuit based on the designed scan chains.